module module_test(
	input CLOCK,
	input RESET,
	
	output TXD,
	input RXD,
	
	output [3:0]LED,
	input KEY2
);

//`define TEST_UART
`define TEST_KEY

`ifdef TEST_UART

wire rxend;
wire [7:0]rxdata;
reg rx_r;
reg startflag;

wire tx_start;
wire [7:0] tx_data;
wire tx_busy;
wire tx_end;

assign tx_data = rxdata + 1'b1;
assign tx_start = startflag;
assign rx_press = rx_r ^ rxend;

uart_tx sendkey(
	.clk(CLOCK),
	.nRST(RESET),
	.tx_start(tx_start),
	.tx_end(tx_end),
	.tx_data(tx_data),
	.tx_busy(tx_busy),
	.tx(TXD)
);

uart_rx revuart(
	.clk(CLOCK),
	.nRST(RESET),
	.rx_end(rxend),
	.rx_data(rxdata),
	.rx_busy(rx_busy),
	.rx(RXD)
);

always @ (posedge CLOCK, negedge RESET)begin
	if(!RESET) begin		
		rx_r <= 1'b0;
	end else begin
		rx_r <= rxend;
	end
end

always @(posedge CLOCK or negedge RESET)begin
	if(!RESET)begin
		startflag <= 1'b0;
	end else begin		
		if(rxend && rx_press) begin
			startflag <= 1'b1;
		end else begin
			startflag <= 1'b0;
		end
	
		
	end 
end

`endif

`ifdef TEST_KEY

reg [3:0]led;
reg key_in_r;
wire keyout;
wire		key_press;
assign key_press = key_in_r ^ keyout;
assign LED = led;

key ctrkey(
	.clk(CLOCK),
	.nRST(RESET),
	.keyin(KEY2),
	.keyout(keyout)
);

always @ (posedge CLOCK, negedge RESET)begin
	if(!RESET) begin							
		key_in_r <= 1'b1;	
	end else begin
		key_in_r <= keyout;
	end
end

always @ (*)begin
	if(keyout == 1'b1)begin
		led = {1'b0 ,1'b0 ,1'b0 ,1'b0};
	end else begin
		led = {1'b1 ,1'b1 ,1'b1 ,1'b1};
	end
end

`endif

endmodule